1. Field of the Invention
The present invention relates to a floating point arithmetic unit in a data processing system and more particularly to a unit that executes a compound instruction A+B.times.C in two cycles that is compatible with the result achieved by executing a multiply instruction followed by an add instruction.
2. Description of the Prior Art
Floating point arithmetic and special units for performing floating point arithmetic are well documented. Floating point numbers in digital data processing machines allow for larger numbers and more complicated scientific applications. A floating point number is comprised of an exponent portion and a mantissa portion. The mantissa portion represents the value of a number and the exponent portion reflects where the radix point is located in relation to the most significant digit of the mantissa. Each digit of a number can be either a binary bit or comprised of four binary bits to represent the value of a hexadecimal digit. Typical data processing systems have a data flow path that is 64 bits wide. An exponent is often eight binary bits and the mantissa 56 bits.
Floating point arithmetic such as multiply or add involve doing the arithmetic on the mantissa portion, but require manipulating the value of the exponent portion either before the operation or subsequent to the operation. When adding two floating point numbers the exponent portion of both operands must be equal. This involves adjusting the number with the smallest exponent by shifting the mantissa portion to the right while incrementing the exponent portion for each shift.
A multiply operation involves multiplying two mantissa portions, often with special hardware, to produce a value that has 112 binary bits. The exponent of the result will be the sum of the exponents of the two numbers.
Rounding and accuracy of floating point numbers is often involved in this arithmetic. Normalized numbers are also desired. A normalized floating point number is characterized by shifting the mantissa and adjusting the exponent by a like amount to achieve a particular value for the most significant digit of the mantissa. The most significant digit is made to have a value the opposite of the binary bit reflecting the sign of the number. The sign of a positive number is a binary 0. In this case the most significant digit of the mantissa must be a non zero. In the case of a binary mantissa the digit must be a binary 1. In the case of hexadecimal numbers, any one of the four binary bits of the hexadecimal number must be a binary 1.
The time required for doing floating point operations is always a concern. General purpose data processing systems, often with just a binary adder, would require many machine cycles. Cycles are needed to manipulate exponents, do the add or multiply, detect leading zero's in the mantissa, shift the mantissa for alignment during an add, shift a result to normalize the mantissa and adjust the exponent. As a result many inventions have been made in the past to provide special purpose hardware that allows much of the mantissa and exponent handling to be accomplished in parallel by predicting leading zero's of results and/or exponents of the result.
Many scientific applications have been found to require a function known as Multiply and Add (MAD). The function would accomplish the formula A+B.times.C. Early on this would be accomplished by executing a multiply instruction to obtain the result B.times.C. This would be followed by adding A to the result product. Even with special purpose hardware to allow for parallel handling of the mantissa and exponent, programming is complicated and the normalizing of results and alignment of operands requires many machine cycles.
The prior art has produced special purpose hardware specifically designed to execute a compound MAD instruction. This is represented by U.S. Pat. No. 4,969,118. Assisting in the execution of compound instructions MAD is a leading zero anticipator circuit described in U.S. Pat. No. 4,926,369. Both of these patents are assigned to the assignee of this invention.
The MAD execution in U.S. Pat. No. 4,969,118 is accomplished in two machine cycles and produces a normalized final result. Accuracy in scientific applications is a very important consideration. It has been found that when the MAD instruction is executed in the hardware of this patent as part of a scientific application, it may not produce a final result equal to the result obtained when the application is run with programming that includes a multiply instruction for doing B.times.C followed by an add instruction for adding A to the result product. This patent does not provide a normalized version of the product during the first cycle of operation that produces the representation of the B.times.C product.